`timescale 1ns/1ps
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// *********************************************************************************
// Project Name : 
// Author       : Dark
// Create Time  : 2023-02-04 10:46:07
// Revise Time	: 2023-02-04 10:46:07
// File Name    : ifetch.sv
// Abstract     :
// -----------------------------------------------------------------------------
`include "defines.svh"
module ifetch(
	input	wire					clk,    // Clock
	input	wire					rst_n,  // Synchronous reset active low
	input 	wire	[31:0]			nextPC, // for irom address
	input 	wire					refetch_flag, 
	
	output 	reg		[31:0]			PC,		//PC register
	output 	wire	[31:0]			instr	// instr fetch	
	);

//=================================================================================
// Signal declaration
//=================================================================================
	wire [31:0] irom_addr; // instr address
//=================================================================================
// Body
//=================================================================================


	assign	irom_addr = {2'b00,PC[31:2]}; // pc in bytes

	always_ff @(posedge clk) begin 
		if(~rst_n) 
			PC <= `PC_BASEADDR;
		else if (~refetch_flag)
			PC <= nextPC;
	end

// inst instruction mem
	ram #(
				.MEMDEEP(`ITCMDEEP)
			) instruction_rom
			(
				.byteena (4'b0000),
				.din     ('d0),
				.rdaddr  (irom_addr),
				.rdclk   (clk),
				.rden    (~refetch_flag),
				.wraddr  ('d0),
				.wrclk   ('d0),
				.wren    (`Disable),
				.dout    (instr)
			);
endmodule
